A group of European electronics companies formed a consortium called the Joint Test Action Group (JTAG). The consortium devised a specification for boundary-scan hardware testing at the IC level. In 1990 the Joint Test Action Group established a standard IEEE 1149.1 that details access to any chip with a so-called JTAG port.
The IEEE 1149.1 JTAG specification uses boundary-scan technology to enable engineers to perform extensive debugging and diagnostics on a system through a small number of dedicated test pins. Signals are scanned into and out of the I/O cells of a device serially to control its inputs and test the outputs under various conditions. Boundary-scan technology is probably the most popular and widely used design-for-test technique in the industry today.
FIG. 1 illustrates a typical prior art set-up including a test system and a device under test (DUT). The test system controls accesses to the DUT via the JTAG ports. In this embodiment, the test system and the DUT are coupled through five lines. The boundary-scan control signals are collectively referred to as the test access port (TAP, not shown). The TASP defines a serial protocol for scan-based devices. There are five pins: TCK, TMS, TDI, TDO and TRST. The TCK, TMS, and TRST input pins drive a 16-state TAP controller (state machine, not shown). The TAP controller manages the exchange of data and instructions. The controller advances to the next state based on the value of the TMS signal at each rising edge of TCK. Pull-up resistors couple to TRST, TMS and TCK lines to power supply Vcc.
Some test equipment and ASIC-cell companies have defined proprietary extensions that use the JTAG capability to implement software debug functions. With the proper support built into a target CPU, this interface may be used to download code, execute it, and examine register and memory values. These functions cover the majority of the low-level functionality of a typical debugger. An inexpensive remote debugger can be run on a workstation or PC to assist in software debugging.
Boundary-scan technology is also used for emulation. FIG. 2 illustrates a prior art test set-up. The emulator front-end acts as the scan manager by controlling the delivery of scan information to and from the device under debug and the debugger window. When a host controls the JTAG scan information, it needs to know if other devices are connected in the scan chain. The JTAG debugger generally duplicates (emulations) the functions of the device under debug. Thus the JTAG debugger behaves like the device under debug or at least can monitor how the device under debug behaves. Controlling the emulation requires an exchange of event related data between the JTAG debugger and the device under debug. In computing an event is defined as an action that is usually initiated outside the scope of a program and that is handled by a piece of code inside the program. Typically events are handled synchronous with the program flow. The program generally has one or more dedicated places where events are handled. The term event covers both synchronous and asynchronous events. An interrupt, which is also regarded as an event, is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. A hardware interrupt causes the processor to save its state of execution via a context switch and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking especially in real-time computing. Typical sources of events include the user pressing a key on the keyboard or hardware devices such as a timer. A computer program that changes its behavior in response to events is said to be event-driven. The goal is often of being interactive. Debugging also requires placing specific breakpoints, jumps or branching within the program flow in the device under debug. This means that events may also relate to interactions of the debugger and the DUT.
FIG. 2 illustrates two additional lines in prior art
JTAG ports coupling the JTAG debugger and the device under debug in order to handle and exchange events. Lines EMU0 and EMU1 exchange events. The JTAG and emulation related data is passed through lines TDO and TDI. Corresponding control signals are passed through lines TMS and TCK. JTAG allows the internal components of the device under test (the CPU, for example) to be scanned using this principle. JTAG may be used to debug embedded devices allowing access to any part of the device that is accessible via the CPU and still test at full speed. This has become a standard emulation debug method used by silicon vendors. This requires numerous extra pins on a device under debug to provide additional system integration capabilities for benchmarking, profiling and system level breakpoints.